The present invention relates to a memory unit. More particularly, the present invention relates to a memory unit for synchronously performing the reading and writing of data by loading a latch used for performing the synchronous read and write of data at a particular location in the sequence of circuit elements and a latch circuit.
FIG. 13 illustrates an example of the conventional apparatus. The conventional apparatus includes an X address input buffer 174 for receiving X address data 172, a Y address input buffer 175 for receiving Y address data 173, and X and Y address input latches 176 and 177, respectively, for taking in and outputting the address data held in the input buffers 174, 175 by use of a first clock signal (CLK1). X and Y predecoders 178 and 179 and X and Y decoders 180 and 181 are provided for decoding the address data from the input latches 176, 177, and X and Y decoder latches 182 and 183 are provided for taking in and outputting the address data from the decoders 180 and 181 by use of a second clock signal (CLK2).
A memory cell array 184 is provided having a predetermined plurality of memory cells in which write data are written via the bit lines. Data held in a predetermined plurality of memory cells are output via bit lines according to the outputs of the X and Y decoder latches 182 and 183. A sense amplifier 185 amplifies a predetermined plurality of output data signals through the bit lines, and a selector 186 selects one data from the plurality of data in the sense amplifier 185 according to the output of the Y decoder latch 183. An output latch 187 is provided for taking in and outputting the data from the selector 186 by use of a third clock signal (CLK3), and an output buffer 188 is provided for holding and outputting the data from the output latch 187.
An input buffer 192 receives write data 190, and a write data input latch 194 takes in and outputs the write data 190 held in the input buffer 192 by use of CLK1. A write data latch 196 takes in and outputs the write data from the write data input latch 194 by use of CLK2. A write circuit 198 writes the data from the write data latch 196 in the memory cells of the memory cell array 184 according to the output of the Y decoder latch 183.
An input buffer 193 receives a control signal 191 and a control signal input latch 195 takes in and outputs the control signal held in the input buffer 193 by use of CLK1. A control signal latch 197 takes in and outputs the control signal from the control signal input latch 195 by use of CLK2, and a read/write control circuit 199 receives the control signal from the control signal latch 197 and outputs signals for controlling the write circuit 198 and the sense amplifier 185. A CLK generating circuit 200 generates the first through third clock signals (CLK1, CLK2, CLK3) fed to the respective latches based on an external clock signal.
FIG. 14 illustrates a simplified flow of address, data and clock signals in the conventional apparatus illustrated in FIG. 13. First, an address is held in an address latch 203 via the input buffer 202. When CLK1 is input to the address latch 203, the address is output from the address latch 203, decoded by the predecoder 204 and the decoder 205, and held in the decoder latch 206. When CLK2 is input to the decoder latch 206, the decoded address is output and a memory cell 207 is selected according to the decoded data. Data is output from the selected memory cell 207 and amplified by the sense amplifier 208. One data out of the amplified data is selected by the selector 209 and held in the output data latch 210. When CLK3 is input to the output data latch 210, data is output outside the chip via the output buffer 211.
FIG. 15 illustrates operating waveforms which exist at the time of performing a reading operation in the conventional apparatus. When an address is received from outside the chip, first the address is held in the address latch 203 via the input buffer 202. Subsequently, CLK1 is input to the address latch 203 at time t1 after the input of the first external clock signal (1st). The address data is output, and the output is held in the decoder latch 206 at time ta. Further, CLK2 is input to the decoder latch 206 at time t2 after the input of the second external clock signal (2nd), and an address decode signal is output. A word line is selected based on the output, and the data is read from the memory cell 207 and amplified by the sense amplifier 208. Then one data is selected by the selector 209 and the data thus selected is held in the output latch 210. The time required during this time is tb.
Lastly, CLK3 is input to the output latch 210 at time t3 after the input of the third external clock signal (3rd), and output data is output. The output data is output from the chip via the output buffer 211 at time tc after time t3. At this time, t3+tc=tack (clock access time). In order to ensure the aforesaid operation, moreover, inequalities t1+ta&lt;tcycle (cycle time)+t2, t2+tb&lt;tcycle+t3 have to be satisfied.
FIG. 16 illustrates operating waveforms which occurs at the time of performing a writing operation in the conventional apparatus. When write data is received from outside the chip, first the write data 190 is held in the write data input latch 194 via the input buffer 192. Subsequently, CLK1 is input to the write data input latch 194 at time t1w after the inputting of the first external clock signal (1st), the write data is output, and the output is held in the write data latch 196 at time taw. Further, CLK2 is input to the write data latch 196 at time t2w after the inputting of the second external clock signal (2nd), and the write data is output. The output is input to the write circuit 198 and written in the memory cell 184 according to the X and Y addresses. The time required during this time is tbw. Consequently, the write time tw is tw=tcycle+t2w+tbw. In order to ensure the aforesaid operation, an equality t1w+taw&lt;tcycle+t2w has to be satisfied.
The above-described circuit of the conventional apparatus is disclosed, for example, in Japanese Patent Laid-Open No. 21786/1989.
The cycle time of the synchronous memory unit is generally restricted by a maximum delay time between the input latch for holding data such as the address signal and the chip selection signal and the output latch for outputting the data. Thus the cycle time cannot be made shorter than the time interval. Accordingly, a system for reducing the latch-to-latch delay time by providing an intermediate latch separately from the input and output latches so as to shorten the cycle time has been proposed and employed in the conventional apparatus.
In the conventional apparatus, however, the latches are provided in a portion where the number of signal lines such as word lines is large, and there is a problem that an increase in the number of latch circuits necessarily results in increasing the chip area. In the case of a 2M-bit CMOS cache SRAM (.times.36), for example, 512 decoder latches are required because there exist 8 X addresses and 8 Y addresses.
Further, in the conventional apparatus two cycles are always needed to write data in a memory cell and consequently the write time cannot be decreased to one-cycle time or less.